1. Field of the Invention
The present invention relates generally to data transfer methods and apparatus and, more particularly, to a method and apparatus for optimizing UDMA data transfer by utilizing UDMA CRC error.
2. Background Information
The speed that data is transferred between a data storage device, such as a hard disk drive, and a computer is critical to the performance of computer systems, such as personal computers. As the processing and memory speeds of the computer increase, improving data transfer rates between the storage device and computer are critical to improving the performance of the computer system.
The computer typically includes a system board, commonly referred to as a motherboard, which includes a CPU, memory, and a support chipset, that includes hardware and software. One well known interface for coupling a hard disk drive to a computer is an Integrated Drive Electronics (IDE)/AT Attachment (ATA) interface. Essentially, an IDE/ATA interface is a standard way for a storage device to connect to a computer, through the use of programmed I/O. In programmed I/O (PIO) the CPU and support hardware directly control the transfer of data between the motherboard and the storage device.
Using PIO, the CPU is responsible for executing the instructions that transfer the data to and from the drive, using special I/O locations. A disadvantage of this technique is that each time a data read or write is needed the CPU is used. This can slow the execution of other operations that the CPU is performing. Thus, the use of PIO modes has become a hindrance to the performance of recently developed hard disk drives.
Direct memory access (DMA) modes were developed to improve upon the performance restrictions of PIO. For example, multiword DMA mode 2, has a maximum data transfer rate of about 16.7 B/s. However, as hard disk drives become faster and faster, DMA is becoming insufficient.
In an effort to overcome the disadvantages of DMA, Ultra DMA (UDMA) modes were developed. With UDMA, data is transferred on both the rising and falling edges of the clock. This is known as double transition clocking. Double transition clocking allows for data throughput of the interface to be doubled for any given clock speed.
Due to the significant data transfer speeds of UDMA, integrity of the UDMA transfer signal becomes problematic. Signal integrity problems may result in data errors. In order to improve the integrity of the UDMA interface, UDMA also introduced the use of cyclical redundancy checking, or CRC, on the interface. With UDMA, a device sending data uses a CRC algorithm to calculate redundant information from each block of data sent over the interface. This CRC information, known as “CRC code” is sent along with the data. On the other end of the interface, a recipient of the data does the same CRC calculation and compares its result to the CRC code delivered by the sender.
A mismatch indicates that data was corrupted and the block of data may need to be resent. A selected number of attempts may be made to resend the corrupted data until error-less data is received by the recipient, depending upon the operating system of the computer system. If errors occur frequently, the computer may determine that there are hardware problems and drop to a slower UDMA mode, or may disable UDMA operation.
A support chipset may be configured to modify the UDMA transfer signal, for generating a signal with an efficient shape for UDMA transfer. This is performed by first measuring the signal. The signal measurements are used to calculate desired parameters that affect the shape of the UDMA transfer related signal. The values of hardware components of the support chipset, such as resistors and capacitors, can be selected or adjusted until the desired shape of the UDMA signal is obtained and the UDMA transfer signal is optimized. The values of these components comprise the desired parameters. Additionally, emerging technologies, such as HDC (Hard Disk Controller) chips have the ability to control slew (slope) of the UDMA signal, as well as setup and holding time.
A disadvantage to this technique is that the parameter that is used for optimizing the UDMA transfer signal can be different for each computer system. Each data storage device and data bus may have different characteristics. This may necessitate the calculation of a different parameter for each computer system. Additionally, coupling a different data storage device to the same computer via the same data bus may generate a different parameter, since the characteristics of the replacement data storage device may be different from the initial data storage device.
Accordingly, there exists a need for a method of optimizing a UDMA transfer signal parameter that functions independently of the computer system.